Efficient management and allocation of hardware resources is essential to the speed, effectiveness and, hence, success in the marketplace of a computer system. Standard computer system architecture calls for a number of special-function electronic subsystems or devices to be interconnected by one or more buses, allowing communication of electronic data between the subsystems or devices. In most computer systems, and in personal computers ("PCs") in particular, the buses represent a precious hardware resource that is allocable to only one communication task at a time. Thus, it is vital that the bus not be allowed to idle or be occupied with communication tasks of less than the most optimal priority.
Among the various electronic devices of the computer system, one is designated as bus master, actively in charge of directing the use of bus resources. In early PCs, the microprocessor central processing unit ("CPU") exclusively played the role of bus master. However, in more recent and sophisticated computer architectures, devices other than the CPU may be equipped with a bus master mode wherein control of the bus from a designated one of the devices is possible. For instance, PCs built around an Industry-Standard Architecture ("ISA") or an Extended Industry-Standard Architecture ("EISA") may be equipped with a Small Computer Systems Interface ("SCSI") controller or network interface controller ("NIC") having a bus master mode. PCs having a bus conforming to Intel's Peripheral Component Interconnect ("PCI") standard may be equipped with an ISA controller, allowing an ISA bus to be appended to the PCI bus.
In all PCs, however, only one device can act as bus master at a given time. Thus, the various devices that can act as bus master are provided with the ability to generate a signal representing a request to be designated as bus master. Bus control circuitry, associated with the bus, grants the requests as they are received, allowing control of the bus to pass among the various possible bus master-capable devices.
Unfortunately, conflicts sometimes arise wherein two or more devices make coincidental or concurrent requests for designation as bus master. To address such possibility, the prior art has provided arbitration circuitry that resolves such conflicts by assigning relative priority to the various devices. Should the bus control circuitry receive coincidental requests, the device having the greatest priority wins and is granted bus master status.
In such prior art systems, this relative priority among the devices is pre-assigned during design of the PC and is static and immutable during the life of the PC. Static pre-assignment of priority causes several problems. First, there may be times during normal operation of a PC during which some devices that have been pre-assigned a low priority require unusually intensive use of the bus. During such times, the assigned priority is inappropriately low, resulting in bus master requests of the unusually active device not being granted and the device being deprived of appropriate use of the bus. Second, the factory-set device priorities are optimized for typical PC use, generally resulting in the CPU receiving by far the highest bus master priority because so many users engage their PCs in CPU-intensive activity. Some users, however, subject their PCs to nonstandard use, perhaps engaging in unusually disk or network-access intensive activities. Unfortunately, although the pre-assigned device priorities are inappropriate, they are immutable. Both of these problems result in loss of system performance and effectiveness, ultimately compromising user acceptance and marketability.
Third, and perhaps most critically, IBM-compatible PCs are open architecture systems wherein slots are provided for the insertion of expansion cards. The open architecture design of such PCs allows for a great number of alternative hardware configurations, but presents a problem for the PC designer in the pre-assignment of device priorities. In short, it is impossible for any one static assignment of priority to result in optimum system performance regardless of hardware configuration. Thus, the prior art static assignment of device priorities during system design is wholly inadequate to ensure the optimum allocation of bus resources among the various devices requesting bus master designation.
Accordingly, what is needed in the art are a circuit and method for arbitration of bus master requests that adapts to changing activity on the part of the devices requesting bus master designation to adjust dynamically the allocation of bus resources in response to differing system demands.